Design of Clock Synchronization of Base Station by Using 8A34002
نویسندگان
چکیده
Abstract The stability of the entire base station depends on synchronization station’s clock. clock management chip 8A34002 supports SyncE Ethernet and IEEE 1588. In this architecture, GPS receiver, SSI, master/slave switching device all emit PPS/TOD signals. signals are input into FPGA, which outputs one signal. signal enters in design scheme, DPLL provides filtering clock-following output. 8A34002‘s output is used as system’s after processing. chip, X86 main control BBU board driven by system clock, serves a reference uses four DPLLs, each for SyncE, PTP, GNSS, test functions.
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ژورنال
عنوان ژورنال: Journal of physics
سال: 2023
ISSN: ['0022-3700', '1747-3721', '0368-3508', '1747-3713']
DOI: https://doi.org/10.1088/1742-6596/2537/1/012008